Integrated circuit (ic) design method, system and program product

ABSTRACT

A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal cell or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

CROSS REFERENCE TO RELATED APPLICATION

The present invention is related to published U.S. application Ser. No.10/917,193, entitled “PHYSICAL DESIGN SYSTEM AND METHOD” to Cohn et al.,published as US 2006/0036977 A1, filed Aug. 12, 2004 and published Feb.16, 2006, and to U.S. application Ser. No. 11/______ (Attorney DocketNo. FIS920070381US1), entitled “GRIDDED GLYPH GEOMETRIC OBJECTS (L3GO)DESIGN METHOD” to Lavin et al., filed coincident herewith, all assignedto the assignee of the present invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to integrated circuit (IC) and chipdesign systems and more particularly to computer aided design (CAD)systems for designing ICs and IC chips.

2. Background Description

A typical integrated circuit (IC) chip includes a stack of severalsequentially formed layers of shapes. Each layer is stacked or overlaidon a prior layer and patterned to form the shapes that define devices(e.g., field effect transistors (FETs)) and wires that connect thedevices into circuits. Each of these layers of shapes, also known asmask levels or just “levels,” may be created or printed opticallythrough well known photolithographic masking, photo-developing and leveldefinition techniques, e.g., etching, implanting, deposition and etc.

Normally, a chip designer creates an electrical and/or logicrepresentation of a new circuit that is converted to a chip/circuitlayout. The chip/circuit layout is converted to mask shapes that areprinted on photolithographic masks. Depending upon the particulardesign, each of these layers may include several hundreds of millions oreven billions of mask shapes. Each photolithographic mask is used toprint a pattern on a semiconductor wafer, which may define local waferproperties or one of the chip/circuit layers. Mask errors translate tochip errors that can cause chip defects. Even the resulting defectivechips are functional, the design may be marginal, reducing chip yield.

Consequently, as these masks become increasingly complex, generatingcomplex masks has become more expensive, requiring increased designcreativity and effort for lithographic patterning and for manipulatingthe design data flow to manufacturing. Thus, manufacturing costs andrisks inherent in making these complex patterns have made ineffectiveand obsoleted some state of the art layout methodologies andcomputer-aided design tools that had otherwise been used.

One approach that has proven effective in simplifying and making thesecomplex designs more manufacturable is in representing portions of aphysical design in a compact format, now known as the gridded glyphgeometric objects (L3GO) format. L3GO is described in Published U.S.patent application No. 2006/0036977 A1, entitled “Physical Design SystemAnd Method” to Cohn et al. Especially where design shapes are relativelyregular, e.g., logic chips with mainly rectangular contacts, diffusions,gates and wring, Cohn et al. has proven effective in reducing the designand manufacturing costs and risks. However, Cohn et al. has not yet beenapplied, effectively, to circuits with features that may be processdependent and require special treatment, e.g., feature-specific designground rules and checking. Such circuits that require special treatmentmay include, for example, Static Random Access Memory (SRAM) cells anddecoupling capacitors, body contacts, diodes, polysilicon resistors,fuses, or bonding pads, e.g., Controlled Collapse Chip Connections(C4s).

Designers use an ad-hoc approach with state of the art SRAM cell design,for example. SRAM cell are designed for compactness (density) and signalbalance. Typically, such an ad-hoc approach results in choosingirregular design shapes that are not easily represented in L3GO format.Likewise fuses require unique spacing to other features and a windowabove each fuse. This requires one or more additional mask steps or, avariation of one or more mask steps, to open the window. Checking thesespecial cases requires checking that is unnecessary for the rest of thedesign. However, state of the art design rule checkers, for example,check the entire chip with compliance with each ground rule, includingthese feature-specific rules.

Consequently, insuring chip-wide compliance with these complicatedfeature-specific rules has reduced productivity. In addition to designereffort in designing to and verifying compliance with (checking) regularground rules, for designers using special case cells (i.e., with thesespecial case circuits), design and compliance is even more complicatedand time consuming. Not only have these feature-specific rulescomplicated ground rule checker coding, for example, ground rule checkerresults have been complicated too and are difficult designers tounderstand. If one cannot understand the ground rule checker results,one cannot identify and fix violations. Moreover, these complicatedrules have hampered design improvements from checking feedback, e.g., toadjust a design as process learning proceeds.

Thus, there is a need for design tools and methods that represent ICcomponents that include specialized, process dependent features in aneffective, useable and understandable format for designers; thatfacilitate faster IC checking (e.g., ground rules) than for the same ICotherwise checked with traditional tools, such as with the ICrepresented in a conventional format; that may be easily integrated intocurrent design entry and flows, especially L3GO; and that facilitates ICdesign improvement after the design is complete.

SUMMARY OF THE INVENTION

It is a purpose of the invention to simplify circuit physical design;

It is yet another purpose of the invention to reduce the cost and riskof layout generation and layout checking of chips with circuits thatinclude features that may be process dependent and require specialtreatment, e.g., feature-specific design ground rules and checking;

It is yet another purpose of the invention to improve the efficiency oflayout data preparation in designs with circuits that include processdependent features that require feature-specific design ground rules andchecking;

It is yet another purpose of the invention to improve the efficiency ofICs that include special case circuits that include features that may beprocess dependent and require special treatment, and are represented ingridded glyph geometric objects (L3GO) format.

The present invention relates to a method of integrated circuit (IC)design, an IC design system and computer program product therefore,e.g., for L3GO designs. Special case cells are cells that representspecialized, process dependent components and are provided as dualrepresentation cells with an internal view and external view. Theexternal view is high level abstract representation that includes accesspins, boundary and possible blocking shapes/layers and optionally,parameterizations. Each external view includes cell to cell spacingrules and connecting and blocking/keepout rules for placement androuting. The internal cell or, internal view includes regular shapesforming cell components and defining cell construction details and areground rule clean by construction or verified by simulation or hardware.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be betterunderstood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

FIGS. 1A-B show an example of a dual representation of a special casecell in a gridded glyph geometric objects (L3GO) format, according to apreferred embodiment of the present invention;

FIG. 2 shows an example of a preferred IC design system for designingICs that include special case cells;

FIG. 3 shows an example of steps in circuit design ICs that includespecial case cells.

DESCRIPTION OF PREFERRED EMBODIMENTS

Turning now to the drawings and, more particularly, FIGS. 1A-B show anexample of a dual representation 100, 102 of a special case cell,according to a preferred embodiment of the present invention. As usedherein, a special case cell includes features that may be processdependent and that require special treatment, e.g., features-specificground rules and checking. Thus special case cells include, for exampleonly, Static Random Access Memory (SRAM) cells and decouplingcapacitors, body contacts, diodes, polysilicon resistors, fuses, orbonding pads, e.g., Controlled Collapse Chip Connections (C4s). Thislist of special case cells is for example only and not intended as alimitation.

Preferably in this example, the special case cell is in an integratedcircuit (IC) chip design in a gridded glyph geometric objects (L3GO)format, such as is described in Published U.S. patent application No.2006/0036977 A1, entitled “Physical Design System And Method” to Cohn etal., assigned to the assignee of the present invention and incorporatedherein by reference. Further, the present invention is described hereinwith reference to L3GO design format for example only and not intendedas a limitation. The present invention has application to reducingresource requirements in any design system or method for any design thatincludes at least one special case cell.

Preferably, each special case cell is provided with two representations,one (external) 100 for use in design and another representations oftarget shapes (internal) 102 substituted for the external cell byelaboration. The external view cell or external cell 100 is a high levelrepresentation that is highly abstract used during the design. Designersuse the external cell 100, preferably exclusively, for placing, checking(e.g., ground rule checking) and routing, extraction, e.g., as describedin Cohn et al., and other design activities. The internal view cell orinternal cell 102 includes glyphs and/or target shapes substituted forthe external cell during hardware extraction and used, e.g., by thetechnology team in other detailed hardware analysis flow. It should benoted that in this example, glyphs are represented by two dimensionalshapes to better visualize cell contents.

The external cell 100 includes any necessary parameterizations,substantially similar to parameterized cells known in the art as pcells.Such parameterizations may include, for example only, body contact,diode, and resistor for width, length. A blockage shape or fence 104dominates the external cell 100 and defines tracks and space wheredesigners can locate outside glyphs/shapes. Each external cell 100includes a cell boundary 106 and pins 108, 110, 112 for externalconnection, e.g., Input/Output (I/O) connections. Also, each pin 108,110, 112 includes identification attributes with an access layer (forthe connection) and a direction, e.g. for an incoming/outgoingconnecting wire 114. Keep out rules define minimum distances frompassing shapes 116 to the fence 104. Cell-to-cell rules maintain aminimum distance between adjacent cells, e.g., cell boundary 106 toadjacent cell boundary 118. These rules may be coded with the cell asattributes, defined with ground rules or both.

The internal cell 102 is previously defined and ground rule clean byconstruction and by compliance with external cell rules. In thisexample, the internal cell 104 includes glyphs and/or target shapes,e.g., rectangle glyphs 120 that define diffusions and a polysiliconstick glyph 122 that defines gates at the diffusions, e.g., the gates atthe diffusions define pass gates. The connecting wire 114 to pin 108connects to internal cell wiring 124, either directly (with both wires114, 124 on the same layer) or, through an inter-level via. Pins 110,112 locate connections or contacts to diffusions. Furthermore, theinternal cell 102 may be an optimized during manufacturing withinconstraints defined by (fixed) external cells 100, transparent todesign. Also, subsequent technology changes contents can be made/appliedto the internal cell 102 without affecting the overall design.

As noted hereinabove, the internal cell 102 includes associatedmodels/parameters that are prefabricated as part of the technology andmay be substituted for the external cell 100 during extraction and otherdetailed analysis flow. For example, during physical to logicalchecking, netlists may be extracted from the internal view. Just as theinternal view would be substituted for mask definition, in the designspace an extraction unit (or other electrical analysis tool) simplysubstitutes that extracted model/netlist for the associated externalview for checking.

FIG. 2 shows an example of a preferred IC design system 130, which maybe the same as the L3GO system of Cohn et al. or any suitable circuitdesign system at least with circuit/logic checking and design rulechecking capabilities. The system 130 also includes a design library 132in storage 134. Though not necessarily referred to as such in the system130, special case cells 136 (in this example including the dualrepresentation 100, 102 of the special case cell of FIGS. 1A-B) may beincluded in the design library 132 or otherwise in storage 134. When,for example, a design is provided, e.g., as a high level logicdefinition, external view cells (e.g., 100) of those special case cells136 are placed and wired as necessary. Thereafter, the IC design ischecked (e.g., checking signal path continuity, logic checking anddesign rule checking) and elaborated.

FIG. 3 shows an example of steps in circuit design according to apreferred embodiment of the present invention. A high level design isprovided in step 142. In step 144 circuits books, e.g., from the designlibrary in storage 134, and external view cells (e.g., 100) of specialcase cells 136 are placed and wired. In a L3GO system, the result is aL3GO layout 146. During DRC in step 148 the external representations arerules checked, checking connections to pins and passing wires forkeepout rules violations. Next is step 150, the design logic and signalpaths are checked normally, based on circuit book contents and internalcell representations, cell placement and wiring. In step 152, if adesign error is found, the layout is adjusted/corrected in step 154. Ifno design errors are found in step 152, then checking continues in step156 until checking is complete. Finally, in step 158 the design iselaborated, substituting the intern al cell for the external, and theelaborated design is sent to the mask house, for example for maskmaking.

Advantageously, preferred dual representation cells (internal view andexternal view cells representing specialized, process dependentcomponents), are easily integrated into L3GO designs, as well as otherstandard design entry systems and design flows, for convenient use bycircuit designers. The external view is high level abstractrepresentation that includes access pins, boundary and possible blockingshapes/layers and optionally, parameterizations. Each external viewincludes cell to cell spacing rules and connecting and blocking/keepoutrules for routing. Standard pin layer ground rules (e.g., power/ground,input/output), are applied to external cells, e.g., 100. The internalcell (e.g., 102) or, internal view includes regular shapes forming cellcomponents and defining cell construction details. Since, the specialrules are previously checked for the internal cells, the internal cellsare ground rule clean by construction. Shapes or circuits contained ineach internal cell need not be checked in a subsequent DRC step, e.g.,as described in Cohn et al. So, the number of design rules to write andcheck for external view cells is reduced; and, the special feature rulesfor internal cell shapes are not checked when the entire design ischecked, reducing the number of rules to check globally. Thus, checkingthe entire design is much simpler and significantly faster thanconventional system, e.g., for ground rule checking.

While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims. It is intended that all such variations andmodifications fall within the scope of the appended claims. Examples anddrawings are, accordingly, to be regarded as illustrative rather thanrestrictive.

1. A method for designing a circuit by representing the elements of adesign for such circuit in electronic form, said method comprising: a)providing an electronic representation of a cell to a design system,said representation being a dual representation cell including anexternal representation comprising connection pin locations and a cellboundary, wherein said pin locations are within or juxtaposed againstsaid cell boundary, said dual representation further including aninternal representation cell corresponding to a device component; and b)connecting an electronic representation of at least one other designelement to said external representation cell to create a circuit designrepresentation.
 2. The method of claim 1 wherein said cellrepresentation further comprises at least one rule prohibiting locationof other design elements within a certain distance of a portion of thecell boundary or prohibiting the location of cells within a certaindistance of each other.
 3. The method of claim 1, further comprisingelectronically checking said circuit design representation against a setof electronically represented design rules to determine whether saiddesign representation is in compliance with said rules.
 4. The method ofclaim 3 wherein none of said design rules is associated only with saidcell except for (A) a rule prohibiting location of other design elementswithin a certain distance of a portion of the cell boundary, and (B) arule prohibiting the location of cells within a certain distance of eachother.
 5. The method of claim 1 wherein said internal representationcell further comprises a description of the electronic functionality ofone or more cell components.
 6. The method of claim 1 furthercomprising: c) providing an elaboration unit for electronicallyconverting said dual representation into a pattern of shapes; d)providing an electronically represented collection of shapes to saidelaboration unit, said collection corresponding to components containedin said cell; and e) elaborating each said internal representation cellinto an electronically represented pattern of shapes, said elaborationcomprising assigning shapes for said each said internal representationcell.
 7. A method of integrated circuit (IC) design comprising the stepsof: a) inputting a circuit design, at least one circuit in said circuitdesign being identified as a special case cell, each said special casecell including an external representation and an internalrepresentation, each said internal representation being in compliancewith design rules; b) checking each said external representation of saideach special case cell for compliance with external cell representationrules; c) modifying said circuit design for any identified violationsfor external cell representation rules; and d) analyzing said circuitdesign for compliance with stated design goals, each said externalrepresentation of said each special case cell being used for design goalanalysis.
 8. A method of IC design as in claim 7, wherein each saidspecial case cell includes at least one feature that is not otherwiseincluded in said circuit design, each said at least one featurerequiring unique ground rules, said unique ground rules not beingapplicable to other circuit features.
 9. A method of IC design as inclaim 7, wherein said circuit design includes a plurality of circuitdesign cells connected together, ones of said plurality of circuitdesign cells being connected to said at least one special case cell, andwherein said each special case cell includes at least one feature not inany of said plurality of circuit design cells.
 10. A method of IC designas in claim 7, wherein said each special case cell includes a cellboundary and at least one pin, said each special case cell connecting tosaid circuit design at each said at least one pin.
 11. A method of ICdesign as in claim 10, wherein said each external representation furtherincludes a fence defining blockage in a respective said cell boundary.12. A method of IC design as in claim 11, wherein the step (b) ofchecking said each external representation comprises design rulechecking (DRC) said design, each said internal representation beingignored during DRC.
 13. A method of IC design as in claim 12, whereinthe step (b) of checking said each external representation furthercomprises checking connection rules to said pins and keepout rules towires adjacent to each said fence.
 14. A method of IC design as in claim13, wherein each said special case cell includes cell attributes andeach of said pins includes attributes for access layers and connectingwire direction.
 15. A method of IC design as in claim 14, wherein thecircuit design is a gridded glyph geometric objects (L3GO) integratedcircuit (IC) design and during elaboration each said external cell isreplaced with a respective said internal cell.
 16. A method of IC designas in claim 7, wherein the step (a) of inputting the circuit designcomprises routing circuit wiring based on placed externalrepresentations.
 17. A method of IC design as in claim 7, wherein atleast one special case cell is a plurality of special case cellincluding Static Random Access Memory (SRAM) cells, decouplingcapacitors, body contacts, diodes, polysilicon resistors, fuses andbonding pads.
 18. A design system for integrated circuit (IC) design,said design system comprising: storage media; a design library in saidstorage media, said design library including a plurality of circuitbooks, each of said circuit books including a design for an IC buildingblock; and at least one special case cell in said design library, eachsaid special case cell including an external representation and aninternal representation, wherein each said external representation ischeckable for compliance with external cell representation rules withother circuit books and for IC design compliance with stated designgoals, each said internal representation being in compliance with designrules.
 19. A design system as in claim 18, wherein each said specialcase cell is a circuit book that includes at least one feature that isnot found in remaining said circuit books, each said at least onefeature complying with unique ground rules, said unique ground rulesbeing inapplicable to other circuit features.
 20. A design system as inclaim 18, wherein each said special case cell includes a cell boundaryand at least one pin, ones of said other circuit books connecting toeach special case cell at each said at least one pin.
 21. A designsystem as in claim 20, wherein each said external representationincludes a fence defining blockage in a respective said cell boundary.22. A design system as in claim 21, wherein during design rule checking(DRC) of said IC design, only DRC compliance with said each externalrepresentation is checked.
 23. A design system as in claim 21 for saideach external representation further comprising connection rules to saidpins and wire keepout rules to each said fence for adjacent wires.
 24. Adesign system as in claim 23, wherein said each special case cellincludes cell attributes and each of said pins includes attributes foraccess layers and connecting wire direction.
 25. A design system as inclaim 24, wherein said plurality of circuit books are in gridded glyphgeometric objects (L3GO) format and include at least one logic circuitand during elaboration each said external cell is replaced with arespective said internal cell.
 26. A design system as in claim 17,wherein said special case cells in said design library include StaticRandom Access Memory (SRAM) cells, decoupling capacitors, body contacts,diodes, polysilicon resistors, fuses and bonding pads.
 27. A computerprogram product for integrated circuit (IC) design, said computerprogram product comprising a computer usable medium having computerreadable program code stored thereon, said computer readable programcode comprising: design library computer readable program code means forproviding each of a plurality of standard circuit books, each of saidstandard circuit books including a design for an IC building block; andcomputer readable program code means for providing one or more specialcase cells, each special case cell comprising: computer readable programcode means for providing an external representation checkable forcompliance with external cell representation rules with other specialcase cells and said standard circuit books, and computer readableprogram code means for providing an internal representation incompliance with stated design goals.
 28. A computer program product asin claim 27, wherein said each special case cell includes featurescomplying with unique ground rules, said unique ground rules not beingapplicable to features in said standard circuit books.
 29. A computerprogram product as in claim 27, wherein said each special case cellincludes a cell boundary and at least one pin for said each special casecell, connection to said each special case cell from ones of saidstandard circuit books and other special case cells being one said atleast one pin.
 30. A computer program product as in claim 29, whereineach said external representation defines a fence defining blockage in arespective said cell boundary.
 31. A computer program product as inclaim 30, wherein during design rule checking (DRC) said IC design, onlyDRC compliance with said each external representation is checked.
 32. Acomputer program product as in claim 30, wherein said each externalrepresentation includes connection rules to said pins and keepout rulesto wires adjacent to each said fence.
 33. A computer program product asin claim 32, wherein said special case cells include attributes for saideach special case cell and for access layers and a connecting wiredirection for each of said pins.
 34. A computer program product as inclaim 33, wherein said plurality of standard circuit books and each saidinternal representation are in gridded glyph geometric objects (L3GO)format and during elaboration each said external cell is replaced with arespective said internal cell.
 35. A computer program product as inclaim 27, wherein said special case cells comprise computer readableprogram code means for providing Static Random Access Memory (SRAM)cells, decoupling capacitors, body contacts, diodes, polysiliconresistors, fuses and bonding pads.